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M29W800AT M29W800AB
8 Mbit (1Mb x8 or 512Kb x16, Boot Block) Low Voltage Single Supply Flash Memory
s
2.7V to 3.6V SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS ACCESS TIME: 80ns PROGRAMMING TIME: 10s typical PROGRAM/ERASE CONTROLLER (P/E.C.) - Program Byte-by-Byte or Word-by-Word - Status Register bits and Ready/Busy Output
1 44
s s s
s s s
SECURITY PROTECTION MEMORY AREA INSTRUCTION ADDRESS CODING: 3 digits MEMORY BLOCKS - Boot Block (Top or Bottom location) - Parameter and Main blocks
TSOP48 (N) 12 x 20mm
SO44 (M)
FBGA
s s
BLOCK, MULTI-BLOCK and CHIP ERASE MULTI BLOCK PROTECTION/TEMPORARY UNPROTECTION MODES ERASE SUSPEND and RESUME MODES - Read and Program another Block during Erase Suspend
LFBGA48 (ZA) 8 x 6 solder balls
s
Figure 1. Logic Diagram
s
LOW POWER CONSUMPTION - Stand-by and Automatic Stand-by 100,000 PROGRAM/ERASE CYCLES per BLOCK 20 YEARS DATA RETENTION - Defectivity below 1ppm/year ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Top Device Code, M29W800AT: D7h - Bottom Device Code, M29W800AB: 5Bh
A0-A18 W E G RP
VCC
s
19
15 DQ0-DQ14 DQ15A-1 M29W800AT M29W800AB BYTE RB
s
s
VSS
AI02599
March 2000
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M29W800AT, M29W800AB
Figure 2. TSOP Connections
A15 A14 A13 A12 A11 A10 A9 A8 NC NC W RP NC NC RB A18 A17 A7 A6 A5 A4 A3 A2 A1 1 48 A16 BYTE VSS DQ15A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0
Figure 3. SO Connections
12 13
M29W800T M29W800B
37 36
RB A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 E VSS G DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11
1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 M29W800T 34 12 M29W800B 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 24 21 22 23
AI02181
RP W A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS DQ15A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC
24
25
AI02179
Table 1. Signal Names
A0-A18 DQ0-DQ7 DQ8-DQ14 DQ15A-1 E G W RP RB BYTE VCC VSS NC DU 2/33 Address Inputs Data Input/Outputs, Command Inputs Data Input/Outputs Data Input/Output or Address Input Chip Enable Output Enable Write Enable Reset/Block Temporary Unprotect Ready/Busy Output Byte/Word Organization Supply Voltage Ground Not Connected Internally Don't Use as Internally Connected
DESCRIPTION The M29W800A is a non-volatile memory that may be erased electrically at the block or chip level and programmed in-system on a Byte-by-Byte or Word-by-Word basis using only a single 2.7V to 3.6V VCC supply. For Program and Erase operations the necessary high voltages are generated internally. The device can also be programmed in standard programmers. The array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. Blocks can be protected against programing and erase on programming equipment, and temporarily unprotected to make changes in the application. Each block can be programmed and erased over 100,000 cycles. Instructions for Read/Reset, Auto Select for reading the Electronic Signature or Block Protection status, Programming, Block and Chip Erase, Erase Suspend and Resume are written to the device in cycles of commands to a Command Interface using standard microprocessor write timings. The device is offered in TSOP48 (12 x 20mm), SO44 and LFBGA48 0.8 mm ball pitch packages.
M29W800AT, M29W800AB
Figure 4. LFBGA Connections (Top view through package)
1 2 3 4 5 6 7 8
F
A13
A12
A14
A15
A16
BYTE
DQ15 A-1
VSS
E
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
D
W
RP
DU
DU
DQ5
DQ12
VCC
DQ4
C
RB
DU
A18
DU
DQ2
DQ10
DQ11
DQ3
B
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
A
A3
A4
A2
A1
A0
E
G
VSS
AI00656
Organisation The M29W800A is organised as 1M x8 or 512K x16 bits selectable by the BYTE signal. When BYTE is Low the Byte-wide x8 organisation is selected and the address lines are DQ15A-1 and A0-A18. The Data Input/Output signal DQ15A-1 acts as address line A-1 which selects the lower or upper Byte of the memory word for output on DQ0-DQ7, DQ8-DQ14 remain at High impedance. When BYTE is High the memory uses the address inputs A0-A18 and the Data Input/Outputs DQ0DQ15. Memory control is provided by Chip Enable E, Output Enable G and Write Enable W inputs. A Reset/Block Temporary Unprotection RP tri-level input provides a hardware reset when pulled Low, and when held High (at VID) temporarily unprotects blocks previously protected allowing them to be programed and erased. Erase and Program operations are controlled by an internal Program/ Erase Controller (P/E.C.). Status Register data output on DQ7 provides a Data Polling signal, and DQ6 and DQ2 provide Toggle signals to indicate the state of the P/E.C operations. A Ready/Busy RB output indicates the completion of the internal algorithms.
Memory Blocks The devices feature asymmetrically blocked architecture providing system memory integration. Both M29W800AT and M29W800AB devices have an array of 19 blocks, one Boot Block of 16 KBytes or 8 KWords, two Parameter Blocks of 8 KBytes or 4 KWords, one Main Block of 32 KBytes or 16 KWords and fifteen Main Blocks of 64 KBytes or 32 KWords. The M29W800AT has the Boot Block at the top of the memory address space and the M29W800AB locates the Boot Block starting at the bottom. The memory maps are showed in Figure 5. Each block can be erased separately, any combination of blocks can be specified for multi-block erase or the entire chip may be erased. The Erase operations are managed automatically by the P/ E.C. The block erase operation can be suspended in order to read from or program to any block not being erased, and then resumed. Block protection provides additional data security. Each block can be separately protected or unprotected against Program or Erase on programming equipment. All previously protected blocks can be temporarily unprotected in the application.
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M29W800AT, M29W800AB
Table 2. Absolute Maximum Ratings (1)
Symbol TA TBIAS TSTG VIO (2) VCC V (A9, E, G, RP) (2) Parameter Ambient Operating Temperature (3) Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage A9, E, G, RP Voltage Value -40 to 85 -50 to 125 -65 to 150 -0.6 to 5 -0.6 to 5 -0.6 to 13.5 Unit C C C V V V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions. 3. Depends on range.
Bus Operations The following operations can be performed using the appropriate bus cycles: Read (Array, Electronic Signature, Block Protection Status), Write command, Output Disable, Stan-by, Reset, Block Protection, Unprotection, Protection Verify, Unprotection Verify and Block Temporary Unprotection. See Tables 5 and 6. Command Interface Instructions, made up of commands written in cycles, can be given to the Program/Erase Controller through a Command Interface (C.I.). For added data protection, program or erase execution starts after 4 or 6 cycles. The first, second, fourth and fifth cycles are used to input Coded cycles to the C.I. This Coded sequence is the same for all Program/Erase Controller instructions. The 'Command' itself and its confirmation, when applicable, are given on the third, fourth or sixth cycles. Any incorrect command or any improper command sequence will reset the device to Read Array mode. Instructions Seven instructions are defined to perform Read Array, Auto Select (to read the Electronic Signature or Block Protection Status), Program, Block Erase, Chip Erase, Erase Suspend and Erase Resume.
The internal P/E.C. automatically handles all timing and verification of the Program and Erase operations. The Status Register Data Polling, Toggle, Error bits and the RB output may be read at any time, during programming or erase, to monitor the progress of the operation. Instructions are composed of up to six cycles. The first two cycles input a Coded sequence to the Command Interface which is common to all instructions (see Table 9). The third cycle inputs the instruction set-up command. Subsequent cycles output the addressed data, Electronic Signature or Block Protection Status for Read operations. In order to give additional data protection, the instructions for Program and Block or Chip Erase require further command inputs. For a Program instruction, the fourth command cycle inputs the address and data to be programmed. For an Erase instruction (Block or Chip), the fourth and fifth cycles input a further Coded sequence before the Erase confirm command on the sixth cycle. Erasure of a memory block may be suspended, in order to read data from another block or to program data in another block, and then resumed. When power is first applied or if VCC falls below VLKO, the command interface is reset to Read Array.
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Table 3. Top Boot Block Addresses, M29W800AT
# 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Size (Kbytes) 16 8 8 32 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address Range (x8) FC000h-FFFFFh FA000h-FBFFFh F8000h-F9FFFh F0000h-F7FFFh E0000h-EFFFFh D0000h-DFFFFh C0000h-CFFFFh B0000h-BFFFFh A0000h-AFFFFh 90000h-9FFFFh 80000h-8FFFFh 70000h-7FFFFh 60000h-6FFFFh 50000h-5FFFFh 40000h-4FFFFh 30000h-3FFFFh 20000h-2FFFFh 10000h-1FFFFh 00000h-0FFFFh Address Range (x16) 7E000h-7FFFFh 7D000h-7DFFFh 7C000h-7CFFFh 78000h-7BFFFh 70000h-77FFFh 68000h-6FFFFh 60000h-67FFFh 58000h-5FFFFh 50000h-57FFFh 48000h-4FFFFh 40000h-47FFFh 38000h-3FFFFh 30000h-37FFFh 28000h-2FFFFh 20000h-27FFFh 18000h-1FFFFh 10000h-17FFFh 08000h-0FFFFh 00000h-07FFFh
Table 4. Bottom Boot Block Addresses, M29W800AB
# 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Size (Kbytes) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 32 8 8 16 Address Range (x8) F0000h-FFFFFh E0000h-EFFFFh D0000h-DFFFFh C0000h-CFFFFh B0000h-BFFFFh A0000h-AFFFFh 90000h-9FFFFh 80000h-8FFFFh 70000h-7FFFFh 60000h-6FFFFh 50000h-5FFFFh 40000h-4FFFFh 30000h-3FFFFh 20000h-2FFFFh 10000h-1FFFFh 08000h-0FFFFh 06000h-07FFFh 04000h-05FFFh 00000h-03FFFh Address Range (x16) 78000h-7FFFFh 70000h-77FFFh 68000h-6FFFFh 60000h-67FFFh 58000h-5FFFFh 50000h-57FFFh 48000h-4FFFFh 40000h-47FFFh 38000h-3FFFFh 30000h-37FFFh 28000h-2FFFFh 20000h-27FFFh 18000h-1FFFFh 10000h-17FFFh 08000h-0FFFFh 04000h-07FFFh 03000h-03FFFh 02000h-02FFFh 00000h-01FFFh
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M29W800AT, M29W800AB
SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs (A0-A18). The address inputs for the memory array are latched during a write operation on the falling edge at Chip Enable E or Write Enable W. In Word-wide organisation the address lines are A0-A18, in Byte-wide organisation DQ15A-1 acts as an additional LSB address line. When A9 is raised to VID, either a Read Electronic Signature Manufacturer or Device Code, Block Protection Status or a Write Block Protection or Block Unprotection is enabled depending on the combination of levels on A0, A1, A6, A12 and A15. Data Input/Outputs (DQ0-DQ7). These Inputs/ Outputs are used in the Byte-wide and Word-wide organisations. The input is data to be programmed in the memory array or a command to be written to the C.I. Both are latched on the rising edge of Chip Enable E or Write Enable W. The output is data from the Memory Array, the Electronic Signature Manufacturer or Device codes, the Block Protection Status or the Status register Data Polling bit DQ7, the Toggle Bits DQ6 and DQ2, the Error bit DQ5 or the Erase Timer bit DQ3. Outputs are valid when Chip Enable E and Output Enable G are active. The output is high impedance when the chip is deselected or the outputs are disabled and when RP is at a Low level. Data Input/Outputs (DQ8-DQ14 and DQ15A- 1). These Inputs/Outputs are additionally used in the Word-wide organisation. When BYTE is High DQ8-DQ14 and DQ15A-1 act as the MSB of the Data Input or Output, functioning as described for DQ0-DQ7 above, and DQ8-DQ15 are 'don't care' for command inputs or status outputs. When BYTE is Low, DQ0-DQ14 are high impedance, DQ15A-1 is the Address A-1 input. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. E High deselects the memory and reduces the power consumption to the stan-by level. E can also be used to control writing to the command register and to the memory array, while W remains at a low level. The Chip Enable must be forced to VID during the Block Unprotection operation. Output Enable (G). The Output Enable gates the outputs through the data buffers during a read operation. When G is High the outputs are High impedance. G must be forced to VID level during Block Protection and Unprotection operations. Write Enable (W). This input controls writing to the Command Register and Address and Data latches. Byte/Word Organization Select (BYTE). The BYTE input selects the output configuration for the device: Byte-wide (x8) mode or Word-wide (x16) mode. When BYTE is Low, the Byte-wide mode is selected and the data is read and programmed on DQ0-DQ7. In this mode, DQ8-DQ14 are at high impedance and DQ15A-1 is the LSB address. When BYTE is High, the Word-wide mode is selected and the data is read and programmed on DQ0-DQ15. Ready/Busy Output (RB). Ready/Busy is an open-drain output and gives the internal state of the P/E.C. of the device. When RB is Low, the device is Busy with a Program or Erase operation and it will not accept any additional program or erase instructions except the Erase Suspend instruction. When RB is High, the device is ready for any Read, Program or Erase operation. The RB will also be High when the memory is put in Erase Suspend or Stan-by modes. Reset/Block Temporary Unprotect Input (RP). The RP Input provides hardware reset and protected block(s) temporary unprotection functions. Reset of the memory is achieved by pulling RP to VIL for at least tPLPX. When the reset pulse is given, if the memory is in Read or Stan-by modes, it will be available for new operations in tPHEL after the rising edge of RP. If the memory is in Erase, Erase Suspend or Program modes the reset will take t PLYH during which the RB signal will be held at VIL. The end of the memory reset will be indicated by the rising edge of RB. A hardware reset during an Erase or Program operation will corrupt the data being programmed or the sector(s) being erased. See Tables 15, 16, and Figure 11. Temporary block unprotection is made by holding RP at VID. In this condition previously protected blocks can be programmed or erased. The transition of RP from VIH to VID must slower than tPHPHH. See Tables 17, 18, and Figure 11. When RP is returned from VID to VIH all blocks temporarily unprotected will be again protected. VCC Supply Voltage. The power supply for all operations (Read, Program and Erase). VSS Ground. VSS is the reference for all voltage measurements.
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DEVICE OPERATIONS See Tables 5, 6 and 7. Read. Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register or the Block Protection Status. Both Chip Enable E and Output Enable G must be low in order to read the output of the memory. A new operation is initiated either on the following edge of Chip Enable E or on any address transition with E at VIL. Write. Write operations are used to give Instruction Commands to the memory or to latch input data to be programmed. A write operation is initiated when Chip Enable E is Low and Write Enable W is Low with Output Enable G High. Addresses are latched on the falling edge of W or E whichever occurs last. Commands and Input Data are latched on the rising edge of W or E whichever occurs first. Output Disable. The data outputs are high impedance when the Output Enable G is High with Write Enable W High. Stan-by. The memory is in stan-by when Chip Enable E is High and the P/E.C. is idle. The power consumption is reduced to the stan-by level and the outputs are high impedance, independent of the Output Enable G or Write Enable W inputs. Automatic Stan-by. After 150ns of bus inactivity (no address transition, CE = VIL) and when CMOS levels are driving the addresses, the chip automatically enters a pseudo-stan-by mode where consumption is reduced to the CMOS stan-by value, while outputs still drive the bus (if G = VIL). Electronic Signature. Two codes identifying the manufacturer and the device can be read from the memory. The manufacturer's code for STMicroelectronics is 20h, the device code is D7h for the M29W800AT (Top Boot) and 5Bh for the M29W800AB (Bottom Boot). These codes allow programming equipment or applications to automatically match their interface to the characteristics of the M29W800A. The Electronic Signature is output by a Read operation when the voltage applied to A9 is at VID and address inputs A1 is Low. The manufacturer code is output when the Address input A0 is Low and the device code when this input is High. Other Address inputs are ignored. The codes are output on DQ0-DQ7. The Electronic Signature can also be read, without raising A9 to VID, by giving the memory the Instruction AS. If the Byte-wide configuration is selected the codes are output on DQ0-DQ7 with DQ8-DQ14 at High impedance; if the Word-wide configuration is selected the codes are output on DQ0-DQ7 with DQ8-DQ15 at 00h. Block Protection. Each block can be separately protected against Program or Erase on programming equipment. Block protection provides additional data security, as it disables all program or erase operations. This mode is activated when both A9 and G are raised to VID and an address in the block is applied on A12-A18. Block protection is initiated on the edge of W falling to VIL. Then after a delay of 100s, the edge of W rising to VIH ends the protection operations. Block protection verify is achieved by bringing G, E, A0 and A6 to VIL and A1 to VIH, while W is at VIH and A9 at VID. Under these conditions, reading the data output will yield 01h if the block defined by the inputs on A12-A18 is protected. Any attempt to program or erase a protected block will be ignored by the device. Block Temporary Unprotection. Any previously protected block can be temporarily unprotected in order to change stored data. The temporary unprotection mode is activated by bringing RP to VID. During the temporary unprotection mode the previously protected blocks are unprotected. A block can be selected and data can be modified by executing the Erase or Program instruction with the RP signal held at VID. When RP is returned to VIH, all the previously protected blocks are again protected. Block Unprotection. All protected blocks can be unprotected on programming equipment to allow updating of bit contents. All blocks must first be protected before the unprotection operation. Block unprotection is activated when A9, G and E are at VID and A12, A15 at VIH. Unprotection is initiated by the edge of W falling to VIL. After a delay of 10ms, the unprotection operation will end. Unprotection verify is achieved by bringing G and E to VIL while A0 is at VIL, A6 and A1 are at VIH and A9 remains at VID. In these conditions, reading the output data will yield 00h if the block defined by the inputs A12-A18 has been successfully unprotected. Each block must be separately verified by giving its address in order to ensure that it has been unprotected.
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M29W800AT, M29W800AB
Table 5. User Bus Operations (1)
Operation Read Word Read Byte Write Word Write Byte Output Disable Stan-by Reset Block Protection (2,4) E VIL VIL G VIL VIL W VIH VIH VIL VIL VIH X X RP V IH V IH V IH V IH V IH V IH VIL BYTE VIH VIL VIH VIL X X X X X A0 A0 A0 A0 A0 X X X X X A1 A1 A1 A1 A1 X X X X X A6 A6 A6 A6 A6 X X X X X A9 A9 A9 A9 A9 X X X V ID V ID A12 A15 A12 A12 A12 A12 X X X X VIH A15 A15 A15 A15 X X X X VIH DQ0DQ7 Data Output Data Output Data Input Data Input Hi-Z Hi-Z Hi-Z X X Block Protect Status(3) Block Protect Status(3) X DQ8DQ14 Data Output Hi-Z Data Input Hi-Z Hi-Z Hi-Z Hi-Z X X DQ15 A-1 Data Output Address Input Data Input Address Input Hi-Z Hi-Z Hi-Z X X
VIL VIH VIL VIH VIL VIH VIH X X X
VIL VID VIL Pulse V IH
Blocks VID VID VIL Pulse V IH Unprotection (4) Block Protection Verify (2,4) Block Unprotection Verify (2,4) Block Temporary Unprotection
Note: 1. 2. 3. 4.
VIL
VIL
VIH
V IH
X
VIL VIH V IL V ID A12
A15
X
X
VIL
VIL
VIH
V IH
X
VIL VIH VIH V ID A12
A15
X
X
X
X
X
V ID
X
X
X
X
X
X
X
X
X
X = VIL or VIH. Block Address must be given an A12-A18 bits. See Table 7. Operation performed on programming equipment.
Table 6. Read Electronic Signature (following AS instruction or with A9 = VID)
Org. Code Manufact. Code Device Code M29W800AT M29W800AB Device E VIL VIL VIL G VIL VIL VIL W V IH V IH V IH BYTE V IH V IH V IH A0 VIL VIH VIH A1 VIL VIL VIL Other Addresses Don't Care Don't Care Don't Care DQ0DQ7 20h D7h 5Bh DQ8DQ14 00h 00h 00h DQ15 A-1 0 0 0
Wordwide
Table 7. Read Block Protection with AS Instruction
Code Protected Block Unprotected Block E VIL VIL G VIL VIL W V IH V IH A0 VIL VIL A1 VIH VIH A12-A18 Block Address Block Address Other Addresses Don't Care Don't Care DQ0-DQ7 01h 00h
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INSTRUCTIONS AND COMMANDS The Command Interface latches commands written to the memory. Instructions are made up from one or more commands to perform Read Memory Array, Read Electronic Signature, Read Block Protection, Program, Block Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are made of address and data sequences. The instructions require from 1 to 6 cycles, the first or first three of which are always write operations used to initiate the instruction. They are followed by either further write cycles to confirm the first command or execute the command immediately. Command sequencing must be followed exactly. Any invalid combination of commands will reset the device to Read Array. The increased number of cycles has been chosen to assure maximum data security. Instructions are initialised by two initial Coded cycles which unlock the Command Interface. In addition, for Erase, instruction confirmation is again preceded by the two Coded cycles. Status Register Bits P/E.C. status is indicated during execution by Data Polling on DQ7, detection of Toggle on DQ6 and DQ2, or Error on DQ5 and Erase Timer DQ3 bits. Any read attempt during Program or Erase command execution will automatically output these five Status Register bits. The P/E.C. automatically sets bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits (DQ0, DQ1 and DQ4) are reserved for future use and should be masked. See Tables 10 and 11. Data Polling Bit (DQ7). When Programming operations are in progress, this bit outputs the complement of the bit being programmed on DQ7. During Erase operation, it outputs a '0'. After completion of the operation, DQ7 will output the bit last programmed or a '1' after erasing. Data Polling is valid and only effective during P/E.C. operation, that is after the fourth W pulse for programming or after the sixth W pulse for erase. It must be performed at the address being programmed or at an address within the block being erased. If all the blocks selected for erasure are protected, DQ7 will be set to '0' for about 100s, and then return to the previous addressed memory data value. See Figure 13 for the Data Polling flowchart and Figure 12 for the Data Polling waveforms. DQ7 will also flag the Erase Suspend mode by switching from '0' to '1' at the start of the Erase Suspend. In order to monitor DQ7 in the Erase Suspend mode an address within a block being erased must be provided. For a Read Operation in Erase Suspend mode, DQ7 will output '1' if the read is attempted on a block being erased and the data value on other blocks. During Program operation in Erase Suspend Mode, DQ7 will have the same behavior as in the normal program execution outside of the suspend mode. Toggle Bit (DQ6). When Programming or Erasing operations are in progress, successive attempts to read DQ6 will output complementary data. DQ6 will toggle following toggling of either G, or E when G is low. The operation is completed when two successive reads yield the same output data. The next read will output the bit last programmed or a '1' after erasing. The toggle bit DQ6 is valid only during P/E.C. operations, that is after the fourth W pulse for programming or after the sixth W pulse for Erase. If the blocks selected for erasure are protected, DQ6 will toggle for about 100s and then return back to Read. DQ6 will be set to '1' if a Read operation is attempted on an Erase Suspend block. When erase is suspended DQ6 will toggle during programming operations in a block different to the block in Erase Suspend. Either E or G toggling will cause DQ6 to toggle. See Figure 14 for Toggle Bit flowchart and Figure 15 for Toggle Bit waveforms.
Table 8. Commands
Hex Code 00h 10h 20h 30h 80h 90h A0h B0h F0h Command Invalid/Reserved Chip Erase Confirm Reserved Block Erase Resume/Confirm Set-up Erase Read Electronic Signature/ Block Protection Status Program Erase Suspend Read Array/Reset
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Table 9. Instructions (1)
Mne. Instr. Cyc. 1+ Read/Reset Memory Array 3+ Addr. (3,7) Data RD (2,4) Byte Addr. (3,7) Word Data Addr. (3,7) Data Addr. (3,7) PG Program 4 Data Byte Word Byte Word Byte Word 555h AAh AAAh 555h AAh AAAh 555h AAh AAAh 555h AAh Byte CE Chip Erase 6 Addr. (3,7) Data ES (10) Erase Suspend Erase Resume 1 Addr. (3,7) Data 1 Addr. (3,7) Data Word AAAh 555h AAh X B0h X 30h 2AAh 55h 555h 2AAh 55h 555h 2AAh 55h 555h 2AAh 55h 555h 2AAh 55h 555h F0h AAAh 555h 90h AAAh 555h A0h AAAh 555h 80h AAAh 555h 80h Read Electronic Signature or Block Protection Status until a new write cycle is initiated. See Note 5 and 6. 1st Cyc. X F0h AAAh 555h AAAh Read Memory Array until a new write cycle is initiated. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc. Read Memory Array until a new write cycle is initiated.
AS
(4)
Auto Select
3+
Program Address Program Data AAAh 555h AAh AAAh 555h AAh
Read Data Polling or Toggle Bit until Program completes.
BE
Block Erase
6
Addr. (3,7) Data
555h 2AAh 55h 555h 2AAh 55h
Block Address 30h AAAh 555h 10h
Additional Block (8) 30h
Note 9
Read until Toggle stops, then read all the data needed from any Block(s) not being erased then Resume Erase. Read Data Polling or Toggle Bits until Erase completes or Erase is suspended another time.
ER
Note: 1. Commands not interpreted in this table will default to read array mode. 2. A wait of tPLYH is necessary after a Read/Reset command if the memory was in an Erase or Program mode before starting any new operation (see Tables 15, 16 and Figure 11). 3. X = Don't Care. 4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the command cycles. 5. Signature Address bits A0, A1, at V IL will output Manufacturer code (20h). Address bits A0 at VIH and A1, at VIL will output Device code. 6. Block Protection Address: A0, at V IL, A1 at VIH and A15-A18 within the Block will output the Block Protection status. 7. For Coded cycles address inputs A11-A18 are don't care. 8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout statuscan be verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered, read Data Polli ng or Toggle bit until Erase is completed or suspended. 9. Read Data Polling, Toggle bits or RB until Erase completes. 10. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.
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M29W800AT, M29W800AB
Table 10. Status Register Bits
DQ Name Logic Level '1' '0' 7 Data Polling DQ DQ '-1-0-1-0-1-0-1-' DQ 6 Toggle Bit '-1-1-1-1-1-1-1-' '1' 5 4 Error Bit '0' Reserved '1' 3 Erase Time Bit '0' Erase Timeout Period On-going Chip Erase, Erase or Erase Suspend on the currently addressed block. Erase Error due to the currently addressed block (when DQ5 = `1'). Program on-going, Erase ongoing on another block or Erase Complete Erase Suspend read on non Erase Suspend block Erase Timeout Period Expired P/E.C. Erase operation has started. Only possible command entry is Erase Suspend (ES). An additional block to be erased in parallel can be entered to the P/E.C. Program or Erase On-going Definition Erase Complete or erase block in Erase Suspend Erase On-going Program Complete or data of non erase block during Erase Suspend Program On-going Erase or Program On-going Program Complete Erase Complete or Erase Suspend on currently addressed block Program or Erase Error Successive reads output complementary data on DQ6 while Programming or Erase operations are on-going. DQ6 remains at constant level when P/E.C. operations are completed or Erase Suspend is acknowledged. This bit is set to `1' in the case of Programming or Erase failure. Indicates the P/E.C. status, check during Program or Erase, and on completion before checking bits DQ5 for program or Erase Success. Note
'-1-0-1-0-1-0-1-'
2
Toggle Bit 1
Indicates the erase status and allows to identify the erased block
DQ 1 0
Note:
Reserved Reserved
Logic level '1' is High, '0' is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
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M29W800AT, M29W800AB
Table 11. Polling and Toggle Bits
Mode Program Erase Erase Suspend Read (in Erase Suspend block) Erase Suspend Read (outside Erase Suspend block) Erase Suspend Program DQ7 DQ7 0 1 DQ6 Toggle Toggle 1 DQ2 1 Note 1 Toggle
DQ7 DQ7
DQ6 Toggle
DQ2 N/A
Note: 1. Toggle if the address is within a block being erased. '1' if the address is within a block not being erased.
Toggle Bit (DQ2). This toggle bit, together with DQ6, can be used to determine the device status during the Erase operations. It can also be used to identify the block being erased. During Erase or Erase Suspend a read from a block being erased will cause DQ2 to toggle. A read from a block not being erased will set DQ2 to '1' during erase and to DQ2 during Erase Suspend. During Chip Erase a read operation will cause DQ2 to toggle as all blocks are being erased. DQ2 will be set to '1' during program operation and when erase is complete. After erase completion and if the error bit DQ5 is set to '1', DQ2 will toggle if the faulty block is addressed. Error Bit (DQ5). This bit is set to '1' by the P/E.C. when there is a failure of programming, block erase, or chip erase that results in invalid data in the memory block. In case of an error in block erase or program, the block in which the error occurred or to which the programmed data belongs, must be discarded. The DQ5 failure condition will also appear if a user tries to program a '1' to a location that is previously programmed to '0'. Other Blocks may still be used. The error bit resets after a Read/Reset (RD) instruction. In case of success of Program or Erase, the error bit will be set to '0'. Erase Timer Bit (DQ3). This bit is set to '0' by the P/E.C. when the last block Erase command has been entered to the Command Interface and it is awaiting the Erase start. When the erase timeout period is finished, after 50s to 90s, DQ3 returns to '1'. Coded Cycles The two Coded cycles unlock the Command Interface. They are followed by an input command or a confirmation command. The Coded cycles consist of writing the data AAh at address AAAh in the Byte-wide configuration and at address 555h in the Word-wide configuration during the first cycle.
During the second cycle the Coded cycles consist of writing the data 55h at address 555h in the Bytewide configuration and at address 2AAh in the Word-wide configuration. In the Byte-wide configuration the address lines A-1 to A10 are valid, in Word-wide A0 to A11 are valid, other address lines are 'don't care'. The Coded cycles happen on first and second cycles of the command write or on the fourth and fifth cycles. Instructions See Table 9. Read/Reset (RD) Instruction. The Read/Reset instruction consists of one write cycle giving the command F0h. It can be optionally preceded by the two Coded cycles. Subsequent read operations will read the memory array addressed and output the data read. A wait state of 10s is necessary after Read/Reset prior to any valid read if the memory was in an Erase mode when the RD instruction is given. The Read/Reset command is not accepted during Erase and erase Suspend. Auto Select (AS) Instruction. This instruction uses the two Coded cycles followed by one write cycle giving the command 90h to address AAAh in the Byte-wide configuration or address 555h in the Word-wide configuration for command set-up. A subsequent read will output the manufacturer code and the device code or the block protection status depending on the levels of A0 and A1. The manufacturer code, 20h, is output when the addresses lines A0 and A1 are Low, the device code, EEh for Top Boot, EFh for Bottom Boot is output when A0 is High with A1 Low. The AS instruction also allows access to the block protection status. After giving the AS instruction, A0 is set to VIL with A1 at VIH, while A12-A18 define the address of the block to be verified. A read in these conditions will output a 01h if the block is protected and a 00h if the block is not protected. Program (PG) Instruction. This instruction uses four write cycles. Both for Byte-wide configuration and for Word-wide configuration. The Program command A0h is written to address AAAh in the Byte-wide configuration or to address 555h in the Word-wide configuration on the third cycle after two Coded cycles. A fourth write operation latches the Address on the falling edge of W or E and the Data to be written on the rising edge and starts the P/E.C. Read operations output the Status Register bits after the programming has started. Memory programming is made only by writing '0' in place of '1'. Status bits DQ6 and DQ7 determine if programming is on-going and DQ5 allows verification of any possible error. Programming at an address not in blocks being erased is also possible during erase suspend. In this case, DQ2 will toggle at the address being programmed.
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M29W800AT, M29W800AB
Table 12. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 10ns 0 to 3V 1.5V
1N914 0.8V
Figure 6. AC Testing Load Circuit
Figure 5. AC Testing Input Output Waveform
3.3k DEVICE UNDER TEST 1.5V 0V
AI01417
OUT CL = 30pF or 100pF
3V
CL includes JIG capacitance
AI01968
Table 13. Capacitance (1) (TA = 25 C, f = 1 MHz)
Symbol C IN COUT Parameter Input Capacitance Output Capacitance Test Condition V IN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
Note: Sampled only, not 100% tested.
Table 14. DC Characteristics (TA = 0 to 70C, -20 to 85C or -40 to 85C; VCC = 2.7V to 3.6V)
Symbol ILI ILO ICC1 ICC2 ICC3 ICC4 (1) VIL VIH VOL VOH VID IID VLKO (1) Parameter Input Leakage Current Output Leakage Current Supply Current (Read by Word) Supply Current (Read by Word) Supply Current (Stan-by) Supply Current (Program or Erase) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage CMOS A9 Voltage (Electronic Signature) A9 Current (Electronic Signature) Supply Voltage (Erase and Program lock-out) A9 = VID 2.0 IOL = 1.8mA IOH = -100A V CC -0.4V 11.5 30 12.5 100 2.3 Test Condition 0V VIN V CC 0V VOUT VCC E = VIL, G = VIH, f = 6MHz E = VIL, G = V IL, f = 6MHz E = VCC 0.2V Byte program, Block or Chip Erase in progress -0.5 0.7 VCC 3 4.5 30 Min Typ. Max 1 1 10 10 100 20 0.8 VCC + 0.3 0.45 Unit
A
A mA mA A mA V V V V V A V
Note: 1. Sampled only, not 100% tested.
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M29W800AT, M29W800AB
Table 15. Read AC Characteristics (TA = 0 to 70C, -20 to 85C or -40 to 85C)
M29W800AT / M29W800AB 80 Symbol Alt Parameter Test Conditio n V CC = 3.0V to 3.6V CL = 30pF Min tAVAV tAVQV tAXQX tBHQV tBLQZ tEHQX tEHQZ (1) tELBH tELBL t ELQV (2) t ELQX (1) tGHQX tGHQZ (1) tGLQV (2) tGLQX (1) tPHEL tPLYH (1, 3) tPLPX tRC tACC tOH tFHQV tFLQZ tOH tHZ tELFH tELFL tCE tLZ tOH tDF tOE tOLZ tRH tRRB tREADY tRP Address Valid to Next Address Valid Address Valid to Output Valid Address Transition to Output Transition BYTE Switching High to Output Valid BYTE Switching Low to Output High Z Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Chip Enable to BYTE Switching Low or High Chip Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable High to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition RP High to Chip Enable Low RP Low to Read Mode RP Pulse Width 500 G = VIL G = VIL E = VIL E = VIL E = VIL E = VIL 0 50 10 500 0 0 30 35 0 50 10 G = VIL G = VIL 0 30 5 80 0 0 30 35 E = VIL, G = VIL E = VIL, G = VIL E = VIL, G = VIL 0 50 50 0 30 5 90 80 80 0 50 50 Max 90 VCC = 3.0V to 3.6V CL = 30pF Min 90 90 Max ns ns ns Unit
ns ns ns ns ns ns ns ns ns ns ns ns s ns
Note: 1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV. 3. To be considered only if the Reset pulse is given while the memory is in Erase or Program mode.
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M29W800AT, M29W800AB
Table 16. Read AC Characteristics (TA = 0 to 70C, -20 to 85C or -40 to 85C)
M29W800AT / M29W800AB 100 Symbol Alt Parameter Test Conditio n V CC = 2.7V to 3.6V CL = 30pF Min tAVAV tAVQV tAXQX tBHQV tBLQZ tEHQX tEHQZ (1) tELBH tELBL t ELQV (2) t ELQX (1) tGHQX tGHQZ (1) tGLQV (2) tGLQX (1) tPHEL tPLYH (1, 3) tPLPX tRC tACC tOH tFHQV tFLQZ tOH tHZ tELFH tELFL tCE tLZ tOH tDF tOE tOLZ tRH tRRB tREADY tRP Address Valid to Next Address Valid Address Valid to Output Valid Address Transition to Output Transition BYTE Switching High to Output Valid BYTE Switching Low to Output High Z Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Chip Enable to BYTE Switching Low or High Chip Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable High to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition RP High to Chip Enable Low RP Low to Read Mode RP Pulse Width 500 G = VIL G = VIL E = VIL E = VIL E = VIL E = VIL 0 50 10 500 0 0 30 40 0 50 10 G = VIL G = VIL 0 30 5 100 0 0 30 50 E = VIL, G = VIL E = VIL, G = VIL E = VIL, G = VIL 0 50 50 0 30 5 120 100 100 0 60 60 Max 120 VCC = 2.7V to 3.6V CL = 30pF Min 120 120 Max ns ns ns Unit
ns ns ns ns ns ns ns ns ns ns ns ns s ns
Note: 1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV. 3. To be considered only if the Reset pulse is given while the memory is in Erase or Program mode.
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tAVAV VALID tAVQV tELQV tAXQX tEHQZ tELQX tEHQX tGLQV tGLQX VALID tBHQV tGHQX tGHQZ tELBL/tELBH tBLQZ ADDRESS VALID AND CHIP ENABLE OUTPUT ENABLE DATA VALID
AI02182
M29W800AT, M29W800AB
A0-A18/ A-1
Figure 7. Read Mode AC Waveforms
E
G
DQ0-DQ7/ DQ8-DQ15
BYTE
Note: Write Enable (W) = High.
M29W800AT, M29W800AB
Table 17. Write AC Characteristics, W Controlled (TA = 0 to 70C, -20 to 85C or -40 to 85C)
M29W800AT / M29W800AB 80 Symbol Alt Parameter VCC = 3.0V to 3.6V CL = 30pF Min tAVAV t AVWL tDVWH tELWL tGHWL tPHPHH (1, 2) tPHWL (1) t PLPX tVCHEL tWHDX tWHEH tWHGL tWHRL (1) tWHWL tWLAX tWLWH tVIDR tRSP tRP tVCS tDH tCH tOEH tBUSY tWPH tAH tWP tWC tAS tDS tCS Address Valid to Next Address Valid Address Valid to Write Enable Low Input Valid to Write Enable High Chip Enable Low to Write Enable Low Output Enable High to Write Enable Low RP Rise Time to VID RP High to Write Enable Low RP Pulse Width VCC High to Chip Enable Low Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Output Enable Low Program Erase Valid to RB Delay Write Enable High to Write Enable Low Write Enable Low to Address Transition Write Enable Low to Write Enable High 30 45 35 80 0 35 0 0 500 4 500 50 0 0 0 90 30 45 35 Max 90 VCC = 3.0V to 3.6V CL = 30pF Min 90 0 45 0 0 500 4 500 50 0 0 0 90 Max ns ns ns ns ns ns s ns s ns ns ns ns ns ns ns Unit
Note: 1. Sampled only, not 100% tested. 2. This timing is for Temporary Block Unprotection operation.
Block Erase (BE) Instruction. This instruction uses a minimum of six write cycles. The Erase Set-up command 80h is written to address AAAh in the Byte-wide configuration or address 555h in the Word-wide configuration on third cycle after the two Coded cycles. The Block Erase Confirm command 30h is similarly written on the sixth cycle after another two Coded cycles. During the input of the second command an address within the block to be erased is given and latched into the memory. Additional block Erase Confirm commands and block addresses can be written subsequently to erase other blocks in parallel, without further Coded cycles. The erase will start after the erase timeout period (see Erase Timer Bit DQ3 description).
Thus, additional Erase Confirm commands for other blocks must be given within this delay. The input of a new Erase Confirm command will restart the timeout period. The status of the internal timer can be monitored through the level of DQ3, if DQ3 is '0' the Block Erase Command has been given and the timeout is running, if DQ3 is '1', the timeout has expired and the P/E.C. is erasing the Block(s). If the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts, and the device is reset to Read Array. It is not necessary to program the block with 00h as the P/E.C. will do this automatically before to erasing to FFh. Read operations after the sixth rising edge of W or E output the status register status bits.
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M29W800AT, M29W800AB
Table 18. Write AC Characteristics, W Controlled (TA = 0 to 70C, -20 to 85C or -40 to 85C)
M29W800AT / M29W800AB 100 Symbol Alt Parameter VCC = 2.7V to 3.6V CL = 30pF Min tAVAV t AVWL tDVWH tELWL tGHWL tPHPHH (1, 2) tPHWL (1) t PLPX tVCHEL tWHDX tWHEH tWHGL tWHRL (1) tWHWL tWLAX tWLWH tVIDR tRSP tRP tVCS tDH tCH tOEH tBUSY tWPH tAH tWP tWC tAS tDS tCS Address Valid to Next Address Valid Address Valid to Write Enable Low Input Valid to Write Enable High Chip Enable Low to Write Enable Low Output Enable High to Write Enable Low RP Rise Time to VID RP High to Write Enable Low RP Pulse Width VCC High to Chip Enable Low Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Output Enable Low Program Erase Valid to RB Delay Write Enable High to Write Enable Low Write Enable Low to Address Transition Write Enable Low to Write Enable High 30 45 35 100 0 45 0 0 500 4 500 50 0 0 0 90 30 50 50 Max 120 VCC = 2.7V to 3.6V CL = 30pF Min 120 0 50 0 0 500 4 500 50 0 0 0 90 Max ns ns ns ns ns ns s ns s ns ns ns ns ns ns ns Unit
Note: 1. Sampled only, not 100% tested. 2. This timing is for Temporary Block Unprotection operation.
During the execution of the erase by the P/E.C., the memory accepts only the Erase Suspend ES and Read/Reset RD instructions. Data Polling bit DQ7 returns '0' while the erasure is in progress and '1' when it has completed. The Toggle bit DQ2 and DQ6 toggle during the erase operation. They stop when erase is completed. After completion the Status Register bit DQ5 returns '1' if there has been an erase failure. In such a situation, the Toggle bit DQ2 can be used to determine which block is not correctly erased. In the case of erase failure, a Read/Reset RD instruction is necessary in order to reset the P/E.C. Chip Erase (CE) Instruction. This instruction uses six write cycles. The Erase Set-up command 80h is written to address AAAh in the Byte-wide configuration or the address 555h in the Word-
wide configuration on the third cycle after the two Coded cycles. The Chip Erase Confirm command 10h is similarly written on the sixth cycle after another two Coded cycles. If the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts and the device is reset to Read Array. It is not necessary to program the array with 00h first as the P/E.C. will automatically do this before erasing it to FFh. Read operations after the sixth rising edge of W or E output the Status Register bits. During the execution of the erase by the P/E.C., Data Polling bit DQ7 returns '0', then '1' on completion. The Toggle bits DQ2 and DQ6 toggle during erase operation and stop when erase is completed. After completion the Status Register bit DQ5 returns '1' if there has been an Erase Failure.
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M29W800AT, M29W800AB
Figure 8. Write AC Waveforms, W Controlled
tAVAV A0-A18/ A-1 VALID tWLAX tAVWL E tELWL G tGHWL W tWHWL tDVWH DQ0-DQ7/ DQ8-DQ15 VALID tWHDX tWLWH tWHGL tWHEH
VCC tVCHEL RB tWHRL
AI02183
Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.
Erase Suspend (ES) Instruction. The Block Erase operation may be suspended by this instruction which consists of writing the command B0h without any specific address. No Coded cycles are required. It permits reading of data from another block and programming in another block while an erase operation is in progress. Erase suspend is accepted only during the Block Erase instruction execution. Writing this command during Erase timeout will, in addition to suspending the erase, terminate the timeout. The Toggle bit DQ6 stops toggling when the P/E.C. is suspended. The Toggle bits will stop toggling between 0.1s and 15s after the Erase Suspend (ES) command has been written. The device will then automatically be set to Read Memory Array mode. When erase is
suspended, a Read from blocks being erased will output DQ2 toggling and DQ6 at '1'. A Read from a block not being erased returns valid data. During suspension the memory will respond only to the Erase Resume ER and the Program PG instructions. A Program operation can be initiated during erase suspend in one of the blocks not being erased. It will result in both DQ2 and DQ6 toggling when the data is being programmed. A Read/Reset command will definitively abort erasure and result in invalid data in the blocks being erased. Erase Resume (ER) Instruction. If an Erase Suspend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at any address, and without any Coded cycles.
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M29W800AT, M29W800AB
Table 19. Write AC Characteristics, E Controlled (TA = 0 to 70C, -20 to 85C or -40 to 85C)
M29W800AT / M29W800AB 80 Symbol Alt Parameter VCC = 3.0V to 3.6V CL = 30pF Min tAVAV tAVEL tDVEH tEHDX tEHEL tEHGL tEHRL (1) tEHWH t ELAX tELEH tGHEL tPHPHH (1, 2) tPHWL (1) t PLPX tVCHWL tWLEL tVIDR tRSP tRP tVCS tWS tWC tAS tDS tDH tCPH tOEH tBUSY tWH tAH tCP Address Valid to Next Address Valid Address Valid to Chip Enable Low Input Valid to Chip Enable High Chip Enable High to Input Transition Chip Enable High to Chip Enable Low Chip Enable High to Output Enable Low Program Erase Valid to RB Delay Chip Enable High to Write Enable High Chip Enable Low to Address Transition Chip Enable Low to Chip Enable High Output Enable High Chip Enable Low RP Rise TIme to VID RP High to Write Enable Low RP Pulse Width VCC High to Write Enable Low Write Enable Low to Chip Enable Low 0 45 35 0 500 4 500 50 0 80 0 35 0 30 0 80 0 45 35 0 500 4 500 50 0 Max 90 VCC = 3.0V to 3.6V CL = 30pF Min 90 0 45 0 30 0 90 Max ns ns ns ns ns ns ns ns ns ns ns ns s ns s ns Unit
Note: 1. Sampled only, not 100% tested. 2. This timing is for Temporary Block Unprotection operation.
POWER SUPPLY Power Up The memory Command Interface is reset on power up to Read Array. The device does not accept commands on the first rising edge of W, if both W and E are at VIL with G at VIH during power-up. Any write cycle initiation is blocked when VCC is below VLKO.
Supply Rails Normal precautions must be taken for supply voltage decoupling; each device in a system should have the VCC rail decoupled with a 0.1F capacitor close to the VCC and VSS pins. The PCB trace widths should be sufficient to carry the VCC program and erase currents required.
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M29W800AT, M29W800AB
Table 20. Write AC Characteristics, E Controlled (TA = 0 to 70C, -20 to 85C or -40 to 85C)
M29W800AT / M29W800AB 100 Symbol Alt Parameter VCC = 2.7V to 3.6V CL = 30pF Min tAVAV tAVEL tDVEH tEHDX tEHEL tEHGL tEHRL (1) tEHWH t ELAX tELEH tGHEL tPHPHH (1,2) tPHWL (1) t PLPX tVCHWL tWLEL tVIDR tRSP tRP tVCS tWS tWC tAS tDS tDH tCPH tOEH tBUSY tWH tAH tCP Address Valid to Next Address Valid Address Valid to Chip Enable Low Input Valid to Chip Enable High Chip Enable High to Input Transition Chip Enable High to Chip Enable Low Chip Enable High to Output Enable Low Program Erase Valid to RB Delay Chip Enable High to Write Enable High Chip Enable Low to Address Transition Chip Enable Low to Chip Enable High Output Enable High Chip Enable Low RP Rise TIme to VID RP High to Write Enable Low RP Pulse Width VCC High to Write Enable Low Write Enable Low to Chip Enable Low 0 45 35 0 500 4 500 50 0 100 0 45 0 30 0 90 0 50 50 0 500 4 500 50 0 Max 120 VCC = 2.7V to 3.6V CL = 30pF Min 120 0 50 0 30 0 90 Max ns ns ns ns ns ns ns ns ns ns ns ns s ns s ns Unit
Note: 1. Sampled only, not 100% tested. 2. This timing is for Temporary Block Unprotection operation.
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M29W800AT, M29W800AB
Figure 9. Write AC Waveforms, E Controlled
tAVAV A0-A18/ A-1 VALID tELAX tAVEL W tWLEL G tGHEL E tEHEL tDVEH DQ0-DQ7/ DQ8-DQ15 VALID tEHDX tELEH tEHGL tEHWH
VCC tVCHWL RB tEHRL
AI02184
Note: Address are latched on the falling edge of E, Data is latched on the rising edge of E.
Figure 10. Read and Write AC Characteristics, RP Related
E tPHEL W tPHWL RB
RP
tPLPX tPHPHH tPLYH
AI02091
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M29W800AT, M29W800AB
Table 21. Data Polling and Toggle Bit AC Characteristics (1) (TA = 0 to 70C, -20 to 85C or -40 to 85C)
M29W800AT / M29W800AB 80 Symbol Parameter VCC = 3.0V to 3.6V CL = 30pF Min Chip Enable High to DQ7 Valid (Program, E Controlled) tEHQ7V Chip Enable High to DQ7 Valid (Chip Erase, E Controlled) Chip Enable High to Output Valid (Program) Chip Enable High to Output Valid (Chip Erase) Q7 Valid to Output Valid (Data Polling) Write Enable High to DQ7 Valid (Program, W Controlled) Write Enable High to DQ7 Valid (Chip Erase, W Controlled) Write Enable High to Output Valid (Program) Write Enable High to Output Valid (Chip Erase) 10 1.0 10 1.0 10 1.0 10 1.0 Max 2400 60 2400 60 35 2400 60 2400 60 10 1.0 10 1.0 90 VCC = 3.0V to 3.6V CL = 30pF Min 10 1.0 10 1.0 Max 2400 60 2400 60 35 2400 60 2400 60 s sec s sec ns ms sec s sec Unit
tEHQV tQ7VQV
tWHQ7V
tWHQV
Note: 1. All other timings are defined in Read AC Characteristics table.
Table 22. Data Polling and Toggle Bit AC Characteristics (1) (TA = 0 to 70C, -20 to 85C or -40 to 85C)
M29W800AT / M29W800AB 100 Symbol Parameter VCC = 2.7V to 3.6V CL = 30pF Min Chip Enable High to DQ7 Valid (Program, E Controlled) Chip Enable High to DQ7 Valid (Chip Erase, E Controlled) Chip Enable High to Output Valid (Program) tEHQV tQ7VQV Chip Enable High to Output Valid (Chip Erase) Q7 Valid to Output Valid (Data Polling) Write Enable High to DQ7 Valid (Program, W Controlled) Write Enable High to DQ7 Valid (Chip Erase, W Controlled) Write Enable High to Output Valid (Program) tWHQV Write Enable High to Output Valid (Chip Erase) 10 1.0 10 1.0 10 1.0 10 1.0 Max 2400 60 2400 60 40 2400 60 2400 60 10 1.0 10 1.0 120 VCC = 2.7V to 3.6V CL = 30pF Min 10 1.0 10 1.0 Max 2400 60 2400 60 50 2400 60 2400 60 s sec s sec ns ms sec s sec Unit
tEHQ7V
tWHQ7V
Note: 1. All other timings are defined in Read AC Characteristics table.
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DATA OUTPUT VALID ADDRESS (WITHIN BLOCKS) tAVQV tELQV tEHQ7V tGLQV tWHQ7V DQ7 VALID IGNORE tQ7VQV VALID DATA POLLING READ CYCLES DATA POLLING (LAST) CYCLE MEMORY ARRAY READ CYCLE
AI02185
M29W800AT, M29W800AB
A0-A18/ A-1
E
Figure 11. Data Polling DQ7 AC Waveforms
G
W
DQ7
DQ0-DQ6/ DQ8-DQ15
LAST WRITE CYCLE OF PROGRAM OR ERASE INSTRUCTION
M29W800AT, M29W800AB
Figure 12. Data Polling Flowchart Figure 13. Data Toggle Flowchart
START
START
READ DQ5 & DQ7 at VALID ADDRESS
READ DQ2, DQ5 & DQ6
DQ7 = DATA NO NO
YES
DQ2, DQ6 = TOGGLE YES NO
NO
DQ5 =1 YES READ DQ7
DQ5 =1 YES
READ DQ2, DQ6
DQ7 = DATA NO FAIL
YES
DQ2, DQ6 = TOGGLE YES PASS FAIL
NO
PASS
AI01369 AI01873
Table 23. Program, Erase Times and Program, Erase Endurance Cycles (TA = 0 to 70C; VCC = 2.7V to 3.6V)
M29W800AT / M29W800AB Parameter Min Chip Erase (Preprogrammed, VCC = 2.7V) Chip Erase (VCC = 2.7V) Main Block Erase (VCC = 2.7V) Chip Program (Byte) (1) Chip Program (Word) (1) Byte/Word Program Program/Erase Cycles (per Block) 100,000 Typ 10 15 1.5 10 5 10 10 5 10 Typical after (1) 100k W/E Cycles 10 15 15 Unit Max sec sec sec sec sec s cycles
Note: 1. Excluded the time required to execute bus cycles sequence for program operation.
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VALID tEHQV tAVQV tELQV tGLQV tWHQV STOP TOGGLE VALID IGNORE VALID DATA TOGGLE READ CYCLE DATA TOGGLE READ CYCLE MEMORY ARRAY READ CYCLE
AI02186
M29W800AT, M29W800AB
A0-A18/ A-1
E
Figure 14. Data Toggle DQ6, DQ2 AC Waveforms
G
W
DQ6,DQ2
DQ0-DQ1,DQ3-DQ5,DQ7/ DQ8-DQ15
LAST WRITE CYCLE OF PROGRAM OF ERASE INSTRUCTION
Note: All other timings are as a normal Read cycle.
M29W800AT, M29W800AB
SECURITY PROTECTION MEMORY AREA The M29W800A features a security protection memory area. It consists of a memory block of 256 bytes or 128 words which is programmed in the ST factory to store a unique code that uniquely identifies the part. This memory block can be read by using the Read Security Data instruction (RDS) as shown in Table 24. Table 24. Security Block Instruction
Unlock Cycle Mne. Instr. Read Security Data Cyc. 1st Cyc. Addr. (1) 1 Data (2) B8h AAh Read OTP Data until a new write cycle is initiated. RDS 2nd Cyc.
Read Security Data (RDS) Instruction. This RDS uses a single write cycle instruction: the command B8h is written to the address AAh. This sets the memory to the Read Security mode. Any successive read attempt will output the addressed Security byte until a new write cycle is initiated.
Note: 1. Address bits A10-A19 are don't care for coded address inputs. 2. Data bits DQ8-DQ15 are don't care for coded address inputs.
Figure 15. Security Block Address Table
BYTE Organisation (x8) TOP BOOT BLOCK BOTTOM BOOT BLOCK
000FFh Security Memory Block 00000h Security Memory Block
0E0FFh
0E000h
WORD Organisation (x16) TOP BOOT BLOCK BOTTOM BOOT BLOCK
0007Fh Security Memory Block 00000h Security Memory Block
0E01Fh
0E000h
AI02746
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Table 25. Ordering Information Scheme
Example: Device Type M29 Operating Voltage W = 2.7 to 3.6V Device Function 800A = 8 Mbit (1Mb x8 or 512Kb x16), Boot Block Array Matrix T = Top Boot B = Bottom Boot Speed 80 = 80 ns 90 = 90 ns 100 = 100 ns 120 = 120 ns Package N = TSOP48: 12 x 20 mm M = SO44 ZA = LFBGA48: 0.8 mm pitch Temperature Range 1 = 0 to 70 C 5 = -20 to 85C 6 = -40 to 85 C Optio n T = Tape & Reel Packing
M29W800AT
80
N
1
T
Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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M29W800AT, M29W800AB
Table 26. Revision History
Date November 1998 February 1999 March 1999 First issue Removed TSOP48 Package Reverse Pinout Program, Erase Times and Erase Endurance Cycles change New document template Document type: from Preliminary Data to Data Sheet Program, Erase Times and Endurance Cycles change (Table 23) LFBGA Package Mechanical Data change (Table 29) LFBGA Package Outline drawing change (Figure 18) Program Erase Times change (Table 23) Description
02/09/00
03/06/00
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M29W800AT, M29W800AB
Table 27. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
Symbol A A1 A2 B C D D1 E e L N CP 0.50 0.05 0.95 0.17 0.10 19.80 18.30 11.90 - 0.50 0 48 0.10 mm Typ Min Max 1.20 0.15 1.05 0.27 0.21 20.20 18.50 12.10 - 0.70 5 0.0197 0.0020 0.0374 0.0067 0.0039 0.7795 0.7205 0.4685 - 0.0197 0 48 0.0039 Typ inches Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.7953 0.7283 0.4764 - 0.0276 5
Figure 16. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
A1
L
Drawing is not to scale. 30/33
M29W800AT, M29W800AB
Table 28. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data
mm Symbol Typ A A1 A2 B C D E e H L N CP 0.80 3 1.27 0.10 28.10 13.20 - 15.90 - - 44 0.10 Min 2.42 0.22 2.25 Max 2.62 0.23 2.35 0.50 0.25 28.30 13.40 - 16.10 - - 0.0315 3 0.0500 0.0039 1.1063 0.5197 - 0.6260 - - 44 0.0039 Typ Min 0.0953 0.0087 0.0886 Max 0.1031 0.0091 0.0925 0.0197 0.0098 1.1142 0.5276 - 0.6339 - - inches
Figure 17. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline
A2 B e D
A C CP
N
E
1
H A1 L
SO-b
Drawing is not to scale.
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M29W800AT, M29W800AB
Table 29. LFBGA48 - 8 x 6 balls, 0.8 mm pitch, Package Mechanical Data
mm Symbol Typ A A1 A2 b D D1 ddd e E E1 FD FE SD SE 0.800 6.000 4.000 1.700 1.000 0.400 0.400 - 5.800 - - - - - 9.000 5.600 0.300 0.200 0.750 0.300 8.800 - Min Max 1.350 0.350 1.000 0.550 9.200 - 0.150 - 6.200 - - - - - 0.0315 0.2362 0.1575 0.0669 0.0394 0.0157 0.0157 - 0.2283 - - - - - 0.3543 0.2205 0.0118 0.0079 0.0295 0.0118 0.3465 - Typ Min Max 0.0531 0.0138 0.0394 0.0217 0.3622 - 0.0059 - 0.2441 - - - - - inch
Figure 18. LFBGA48 - 8 x 6 balls, 0.8 mm pitch, Bottom View Package Outline D FD FE SD D1
SE E E1 BALL "A1" ddd
A
e
b A1
A2
BGA-Z00
Drawing is not to scale.
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M29W800AT, M29W800AB
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A . http://w ww.st.com
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